1. Field of the Invention
The present invention relates to a clock supply device which supplies a reference clock to a transmission device, such as an optical transmission device or mobile communications device, which is provided in a digital synchronous network. In particular, the present invention relates to a clock supply device which comprises a plurality of clock supply boards which generate clock signals based on an external reference clock supplied from an upper level of the digital synchronous network, whereby these clock supply boards create a redundant configuration.
2. Description of the Related Art
A reference clock source which act as a reference is provided in the uppermost layer of a digital synchronous network, and a standard cesium oscillator is generally used as this reference clock source. Each transmission device within the synchronous network comprises a unit (hereinafter called a “system clock supply device”) which generates a system clock to be used within that device, based on a clock which is supplied from that reference clock source.
The system clock supply device could be considered to be the heart of a transmission device, and a breakdown in the system clock would cause an immediate system failure. For that reason, the system clock supply device is made to have a redundant configuration, in order to provide stable service in a communications device or the like which could cause serious trouble by failing.
A plurality of clock supply units is provided in a redundant system clock supply device; one of these is used to supply the current clock signal as an active unit (ACT unit) and the other clock supply unit acts as a standby unit (STBY unit).
An example of the redundant configuration of a system clock supply device of the prior art is shown in FIG. 1.
A system clock supply device 1 comprises a plurality of clock supply units 10 and 20 which each generate a clock signal based on an external reference clock, and the redundant configuration is implemented by using one unit as the active unit while another unit is on standby as a standby unit.
The first clock supply unit 10 comprises a reference clock selector 11 which selects one clock signal, with which that unit 10 is synchronized, from external reference clock signals which are supplied from N lines from a clock supply source of a higher level; a digital phase locked loop circuit (DPLL) 12 which generates a predetermined clock signal based on that external reference clock; and an analog phase locked loop circuit (APLL) 13 which generates a clock signal of a frequency higher than that of the clock signal generated by the DPLL 12. The second clock supply unit 20 has a structure similar to that of the first clock supply unit 10, that is, the second clock supply unit 20 comprises a reference clock selector 21, a DPLL 22, and an APLL 23.
The first clock supply unit 10 also comprises an output clock selector 15. The output clock selector 15 selects either a clock signal from the DPLL 12 of the self unit or a clock signal from the DPLL 22 of the second clock supply unit 20, which has been input thereto from the second clock supply unit 20 through back-board wiring B2, as the output clock signal which the first clock supply unit 10 outputs, for input to a distribution PLL 16.
Note that, in this document, the clock signal which has been input from the second clock supply unit 20 through the back-board wiring B2 to the first clock supply unit 10 is called the “partner clock signal” in descriptions relating to the first clock supply unit 10.
The distribution PLL 16 inputs the clock signal which has been selected by the output clock selector 15, generates a clock signal synchronized with that clock signal, and outputs that to an electronic device 2.
When the output clock selector 15 has switched the output clock signal which is output from the first clock supply unit 10 from one of the clock signal from the DPLL 12 and the partner clock signal to the other, the distribution PLL 16 smoothes any sudden phase change in the output clock signal caused by any phase difference between the two clock signals.
If a problem occurs in the active unit which is currently being used, the distribution PLL 16 also fulfills the role of continuing the supply of the clock signal to the electronic device 2 in the later stage by self-oscillation during the short period of time until the switchover operation of the output clock selector 15 is completed, even if the input of the clock signal from the DPLL of the active unit has ceased.
Note that the second clock supply unit 20 has a similar configuration to that of the first clock supply unit 10, that is, the second clock supply unit 20 comprises an output clock selector 25 and a distribution PLL 26. The clock signal from the DPLL 12 of the clock supply unit 10 is input into the second clock supply unit 20 through back-board wiring B1.
Note that, in this document, the clock signal which has been input from the first clock supply unit 10 through the back-board wiring B1 to the second clock supply unit 20 is called the “partner clock signal” in descriptions relating to the second clock supply unit 20.
In this case, the expression “the clock signal from the”, within phrases such as “the clock signal from the DPLL 12” and “the clock signal from the DPLL of the self unit” which are used in this document and in the descriptions of the claims, is used to indicate which of the clock supply units has the DPLL which generates the clock signal in which the target clock signal originates. For example, the target clock signal in the above expression may be the clock signal generated by that DPLL directly, a clock signal generated by a later-stage APLL based on the clock signal generated by the DPLL directly, and a clock signal which is one of those signals which has been delayed by a known delay line.
To indicate the clock signal which is generated by the DPLL directly, on the other hand, expressions such as “the clock signal generated by” the DPLL 12 or “the output clock signal of” the DPLL 22 of the second clock supply unit 20.
The system clock supply device 1 performs the operation of switching one of the clock supply units 10 and 20 from being the active unit to being the standby unit, and the other from being the standby unit to being the active unit, by means of the two output clock selectors 15 and 25.
When the first clock supply unit 10 is the active unit and the second clock supply unit 20 is the standby unit, as shown in FIG. 1 by way of example, the clock signal from the DPLL 12 of the first clock supply unit 10 is output from the clock supply unit 10 while the partner clock signal from the DPLL 12 of the first clock supply unit 10 is also output from the second clock supply unit 20.
Conversely, when the second clock supply unit 20 is the active unit and the first clock supply unit 10 is the standby unit, the clock signal from the DPLL 22 of the second clock supply unit 20 is output from the clock supply unit 20 while the partner clock signal from the DPLL 22 of the second clock supply unit 20 is also output from the first clock supply unit 10.
To ensure that there is no phase difference between the clock signals supplied from the two units 10 and 20 due to a delay in the back-board wiring between the first clock supply unit 10 and the second clock supply unit 20 delay lines 14 and 24, which have delays corresponding to the delays of the back-board wiring, are provided between the APLL 13 of the first clock supply unit 10 and the output clock selector 15 and between the APLL 23 of the second clock supply unit 20 and the output clock selector 25, respectively.
The switchover operations of the two output clock selectors 15 and 25 is controlled by an active-system switching signal which is generated by an active-system switcher portion 40 provided within the system clock supply device 1 or provided in an external device at a level higher than that of the system clock supply device 1. The active-system switcher portion 40 detects an abnormality in the output clock of the active unit, for example, then automatically switches the state of the unit which was being used as the active unit from active state to standby state and switches the state of the unit which was on standby as the standby unit from standby state to active state. The active-system switcher portion 40 also can also be set to do this switchover in answer to a manual operation by the operator.
The electronic device 2 which uses the clock signal supplied from the system clock supply device 1 comprises a unit selector 31, which selects one of the two clock supply units 10 and 20 as the active unit and receive the clock signal supplied by the selected unit, and a PLL 32 which generates a clock signal to be used within that device 2, based on the clock signal which is received from the thus-selected active unit.